The current I'm reading is the same in power down mode whether or not the internal pull-ups are enabled. Refer to ”DIDR1 – Digital Input Disable Register 1” on page 236 and ”DIDR0 – Digital Input Disable Register 0” on page 251 for details.īut I just tried to duplicate his result and I don't see what he measured. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. For analog input pins, the digital input buffer should be disabled at all times. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. Refer to the section ”Digital Input Enable and Sleep Modes” on page 79 for details on which pins are enabled. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. This ensures that no power is consumed by the input logic when not needed. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. The most important is then to ensure that no pins drive resistive loads. When entering a sleep mode, all port pins should be configured to use minimum power. That would be totally absurd and is clearly not the case! I would guess that it's because in sleep mode inputs are clamped to ground.
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